The present invention is related generally to the field of workpiece processing such as, for example, processing semiconductor wafers and, more particularly, to a multi-workpiece processing chamber and its method of use.
A number of processing systems, currently used in the production of semiconductor wafers, are capable of processing more than one wafer at a time for purposes of enhancing system throughput. It has been asserted in the prior art, however, that a single-wafer process chamber provides more uniform process results when compared to multi-wafer processing chamber configurations. Presumably, this degradation in “across-wafer” and “station-to-station” uniformity is thought to be directly attributable to communication between adjacent wafer processing stations within a shared process chamber and environment.
Process uniformity, however, is of increasing concern, particularly in view of an industry emphasis on ever-decreasing device feature sizes. One example, attempting to provide a compromise between the asserted contamination problem that is associated with batch processing in a shared process environment and limited throughput in the use of single-wafer process chamber, is seen in U.S. Pat. No. 5,855,681 (hereinafter the '681 patent). The latter adopts the use of “tandem” single wafer processing chambers, having processing regions that are described as being separate from one another (see col. 4, ln. 37-40). A single chamber body is used to define these separate processing regions. The processing region defined by each tandem chamber is deemed by the patent as isolatable from the processing region of the other tandem chamber by virtue of limiting communication between the adjacent processing regions only to that which selectively occurs through an exhaust system. Such selective communication would presumably be controlled based on the pumping status of the vacuum pumping system. Otherwise, the tandem chambers appear to function, from a process standpoint, in a way which is essentially the same as a pair of separate single-wafer processing chambers (see, for example, col. 2, ln. 54-56). In this regard, the system provides for multiple, isolated processes to be performed concurrently in at least two regions (see col. 4, ln. 44-51), which reasonably suggests that a first process can be performed in one processing region of a tandem chamber while a second, different process is performed in the other processing region of that same tandem chamber.
While there may be advantages associated with the asserted capabilities of the separate, tandem chambers of the '861 patent in providing for simultaneously executing different processes in each chamber, it is a concern that there are many circumstances in which such capability is not necessary. That is, there are many instances in which it is advantageous, at least from a throughput standpoint, to perform the same process at both processing stations, without a need for providing the additional capability to practice different processes. It is a further concern that certain aspects of the configuration for the tandem chamber of the '861 patent such as, for example, its exhaust configuration, are quite complex. This exhaust system is seen in FIG. 21 of the patent wherein a pair of individual exhaust conduits 621 merge into a common exhaust channel 619. It is considered that the use of this complex exhaust system adds considerable expense to the fabrication of the tandem chamber arrangement. Still further problems could be introduced if there is any tendency for contaminants to build up in exhaust channels 621, leading to different pressures in one chamber with respect to the other. Likewise, other features, which result in the capability to practice different processes, are considered to add expense to the cost of the system in order to achieve a level of region-to-region process isolation which may never be needed, in view of a particular end user's needs.
Referring to FIG. 1, one prior art process chamber configuration, that has been found to be useful and which avoids the aforedescribed concerns with respect to the '681 patent, is generally indicated by the reference number 10. Chamber 10 includes a first wafer pedestal 12 and a second wafer pedestal 14, each of which is configured for supporting a wafer (not shown) thereon.
Referring to FIG. 2 in conjunction with FIG. 1, chamber 10 includes a chamber base 20 that is best seen in the cross-sectional view of FIG. 2 and is integrally formed with an arrangement of sidewalls 22. Chamber base 20 defines a single exhaust port 24 which serves the entire chamber interior. A single chamber lid (not shown) is hinged to chamber 10 along one of its peripheral edges and seals against an O-ring 28 (FIG. 1) that is supported by sidewall arrangement 22. A partition 30 is integrally formed with sidewalls 22 and with chamber base 20 so as to extend between a lengthwise pair of the sidewalls, across the entrance leading into exhaust port 24. A notch 32 is defined in partition 30 so as to provide for flow communication between opposing sides of the partition. A pump spool 34 is attached to chamber base 20 and defines an exhaust channel 36 that is aligned with exhaust port 24.
Referring to FIG. 2, partition 30 does not seal against chamber lid 26. In this regard, a gap (not shown) is formed between an upper edge of the partition and the chamber lid so that the upper edge confronts the chamber lid, but does not contact it. Such potential rubbing contact is undesirable at least for the reason that particle generation would occur in a way that can adversely affect a process that is being executed at either of the wafer pedestals in the chamber. Partition 30 has a thickness that is on the order of ¼ or less of the thickness of the chamber sidewalls. Accordingly, the partition is not intended to support a pressure differential from one side to the other, since continuous pressure equalization occurs very rapidly through notch 32. It should be appreciated that even slight pressure differences from one processing station to the other can produce significant differences in on-wafer process results.
Referring again to FIG. 1, chamber 10 is considered to comprise a batch processing system, since no capability is provided for performing a different process at wafer pedestal 12 than the process which is preformed at wafer pedestal 14. That is, either the same process should be performed at both pedestals or one of the pedestals should be inactive. This system will not accommodate performing different processes at the pedestals, since some degree of cross-contamination can occur. At the same time, however, it is recognized that this limited level of cross-contamination may be insignificant when the same process is performed at multiple stations that are within a common process chamber and environment.
Of course, some process constraints can be controlled individually for each wafer pedestal, as has long been practiced. For example, variations in gas mixtures intended to further enhance process uniformity can be provided using separate showerheads (not shown), one of which is provided for each wafer pedestal.
The chamber of FIGS. 1 and 2 has provided more than acceptable process results while avoiding the need to use completely isolated single wafer process environments, as is taught by the '228 patent. In this regard, the present invention provides more than acceptable process results in a multi-wafer chamber maintaining a limited communication between adjacent processing regions, which continues to overcome the aforementioned concerns associated with the '228 patent, while providing still further advantages over all prior art of which Applicant is aware, as will be described in detail hereinafter.